<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>AXI on 0xMax42 - Flatfile purist. Autodidact. Systems thinker.</title><link>https://0xMax42.io/en/tags/axi/</link><description>Recent content in AXI on 0xMax42 - Flatfile purist. Autodidact. Systems thinker.</description><generator>Hugo -- gohugo.io</generator><language>en</language><lastBuildDate>Sat, 19 Apr 2025 19:14:03 +0000</lastBuildDate><atom:link href="https://0xMax42.io/en/tags/axi/index.xml" rel="self" type="application/rss+xml"/><item><title>Minimal Skidbuffer with AXI-like Handshaking</title><link>https://0xMax42.io/en/p/minimal-skidbuffer-with-axi-like-handshaking/</link><pubDate>Sat, 19 Apr 2025 19:14:03 +0000</pubDate><guid>https://0xMax42.io/en/p/minimal-skidbuffer-with-axi-like-handshaking/</guid><description>&lt;img src="https://0xMax42.io/p/minimaler-skidbuffer-mit-axi-like-handshaking/cover.webp" alt="Featured image of post Minimal Skidbuffer with AXI-like Handshaking" /&gt;&lt;p&gt;Created in less than an hour:&lt;br&gt;
A compact skidbuffer that &lt;strong&gt;only decouples the &lt;code&gt;ready&lt;/code&gt; signal&lt;/strong&gt; – with zero added latency.&lt;/p&gt;
&lt;p&gt;The background here is the use of &lt;strong&gt;AXI-like handshaking&lt;/strong&gt; and the need to decouple the &lt;code&gt;ready&lt;/code&gt; signal in order to optimize data processing. In the desisngs I use, the &lt;code&gt;ready&lt;/code&gt; signal is often the bottleneck, as it usually has to be propagated through several pipelines. A skid buffer can help here to reduce latency and optimize data processing. In contrast, the ‘valid’ signal is not decoupled as it is decoupled by each pipeline itself.&lt;/p&gt;
&lt;p&gt;Translated with DeepL.com (free version)&lt;/p&gt;
&lt;p&gt;The design follows a simple principle:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;If &lt;code&gt;ready = '1'&lt;/code&gt;, the signal is passed through directly (&lt;code&gt;MUX = 0&lt;/code&gt;)&lt;/li&gt;
&lt;li&gt;If &lt;code&gt;ready = '0'&lt;/code&gt;, a buffer is activated (&lt;code&gt;MUX = 1&lt;/code&gt;)&lt;/li&gt;
&lt;li&gt;&lt;code&gt;valid&lt;/code&gt; is either forwarded directly or taken from the buffer&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;The system implements complete &lt;strong&gt;AXI-like handshaking&lt;/strong&gt;&lt;br&gt;
and was successfully tested with randomly delayed upstream and downstream.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Resource usage (after synthesis, Xilinx Spartan-3):&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;1 flip-flop&lt;/li&gt;
&lt;li&gt;4 LUTs&lt;/li&gt;
&lt;li&gt;0 added latency&lt;/li&gt;
&lt;/ul&gt;
&lt;hr&gt;
&lt;div class="highlight"&gt;&lt;div class="chroma"&gt;
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&lt;pre tabindex="0" class="chroma"&gt;&lt;code class="language-vhdl" data-lang="vhdl"&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="c1"&gt;--@ Set mux to buffered mode if data is available in the buffer.&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="n"&gt;C_MUX&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="c1"&gt;--@ Enable the buffer register if not buffered and chip enable is high.&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="n"&gt;C_Enable&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="n"&gt;I_CE&lt;/span&gt; &lt;span class="k"&gt;and&lt;/span&gt; &lt;span class="k"&gt;not&lt;/span&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="c1"&gt;--@ Set the ready signal to high if not buffered.&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="n"&gt;O_Ready&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="k"&gt;not&lt;/span&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="c1"&gt;--@ Set the valid signal to high if data is available in the buffer or if data is valid.&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="n"&gt;O_Valid&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt; &lt;span class="k"&gt;or&lt;/span&gt; &lt;span class="n"&gt;I_Valid&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="k"&gt;process&lt;/span&gt; &lt;span class="p"&gt;(&lt;/span&gt;&lt;span class="n"&gt;I_CLK&lt;/span&gt;&lt;span class="p"&gt;)&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="k"&gt;begin&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;if&lt;/span&gt; &lt;span class="n"&gt;rising_edge&lt;/span&gt;&lt;span class="p"&gt;(&lt;/span&gt;&lt;span class="n"&gt;I_CLK&lt;/span&gt;&lt;span class="p"&gt;)&lt;/span&gt; &lt;span class="k"&gt;then&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;if&lt;/span&gt; &lt;span class="n"&gt;I_RST&lt;/span&gt; &lt;span class="o"&gt;=&lt;/span&gt; &lt;span class="n"&gt;G_ResetActiveAt&lt;/span&gt; &lt;span class="k"&gt;then&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;0&amp;#39;&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;elsif&lt;/span&gt; &lt;span class="n"&gt;I_CE&lt;/span&gt; &lt;span class="o"&gt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;1&amp;#39;&lt;/span&gt; &lt;span class="k"&gt;then&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;if&lt;/span&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt; &lt;span class="o"&gt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;0&amp;#39;&lt;/span&gt; &lt;span class="k"&gt;and&lt;/span&gt; &lt;span class="n"&gt;I_Valid&lt;/span&gt; &lt;span class="o"&gt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;1&amp;#39;&lt;/span&gt; &lt;span class="k"&gt;then&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;1&amp;#39;&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;elsif&lt;/span&gt; &lt;span class="n"&gt;I_Ready&lt;/span&gt; &lt;span class="o"&gt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;1&amp;#39;&lt;/span&gt; &lt;span class="k"&gt;and&lt;/span&gt; &lt;span class="p"&gt;(&lt;/span&gt;&lt;span class="n"&gt;R_IsBuffered&lt;/span&gt; &lt;span class="k"&gt;or&lt;/span&gt; &lt;span class="n"&gt;I_Valid&lt;/span&gt;&lt;span class="p"&gt;)&lt;/span&gt; &lt;span class="o"&gt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;1&amp;#39;&lt;/span&gt; &lt;span class="k"&gt;then&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="n"&gt;R_IsBuffered&lt;/span&gt; &lt;span class="o"&gt;&amp;lt;=&lt;/span&gt; &lt;span class="sc"&gt;&amp;#39;0&amp;#39;&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;end&lt;/span&gt; &lt;span class="k"&gt;if&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;end&lt;/span&gt; &lt;span class="k"&gt;if&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt; &lt;span class="k"&gt;end&lt;/span&gt; &lt;span class="k"&gt;if&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;span class="line"&gt;&lt;span class="cl"&gt;&lt;span class="k"&gt;end&lt;/span&gt; &lt;span class="k"&gt;process&lt;/span&gt;&lt;span class="p"&gt;;&lt;/span&gt;
&lt;/span&gt;&lt;/span&gt;&lt;/code&gt;&lt;/pre&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/table&gt;
&lt;/div&gt;
&lt;/div&gt;&lt;hr&gt;
&lt;p&gt;&lt;img src="https://0xMax42.io/p/minimaler-skidbuffer-mit-axi-like-handshaking/40bf09d4ab0c.drawio.webp"
width="5502"
height="3264"
srcset="https://0xMax42.io/p/minimaler-skidbuffer-mit-axi-like-handshaking/40bf09d4ab0c.drawio_hu_c343e3172592ff3a.webp 480w, https://0xMax42.io/p/minimaler-skidbuffer-mit-axi-like-handshaking/40bf09d4ab0c.drawio_hu_d9e55a6741a1a205.webp 1024w"
loading="lazy"
alt="Skidbuffer Block Diagram"
class="gallery-image"
data-flex-grow="168"
data-flex-basis="404px"
&gt;&lt;/p&gt;
&lt;hr&gt;
&lt;p&gt;This architecture is especially suited for deep pipeline systems with timing bottlenecks on ready.&lt;/p&gt;
&lt;p&gt;No overhead – just data flow.&lt;/p&gt;</description></item></channel></rss>