Created in less than an hour:
A compact skidbuffer that only decouples the ready signal – with zero added latency.

The background here is the use of AXI-like handshaking and the need to decouple the ready signal in order to optimize data processing. In the desisngs I use, the ready signal is often the bottleneck, as it usually has to be propagated through several pipelines. A skid buffer can help here to reduce latency and optimize data processing. In contrast, the ‘valid’ signal is not decoupled as it is decoupled by each pipeline itself.

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The design follows a simple principle:

• If ready = '1', the signal is passed through directly (MUX = 0)
• If ready = '0', a buffer is activated (MUX = 1)
• valid is either forwarded directly or taken from the buffer

The system implements complete AXI-like handshaking
and was successfully tested with randomly delayed upstream and downstream.

Resource usage (after synthesis, Xilinx Spartan-3):

• 1 flip-flop
• 4 LUTs
• 0 added latency

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--@ Set mux to buffered mode if data is available in the buffer.
C_MUX    <= R_IsBuffered;
--@ Enable the buffer register if not buffered and chip enable is high.
C_Enable <= I_CE and not R_IsBuffered;
--@ Set the ready signal to high if not buffered.
O_Ready  <= not R_IsBuffered;
--@ Set the valid signal to high if data is available in the buffer or if data is valid.
O_Valid  <= R_IsBuffered or I_Valid;

process (I_CLK)
begin
    if rising_edge(I_CLK) then
        if I_RST = G_ResetActiveAt then
            R_IsBuffered <= '0';
        elsif I_CE = '1' then
            if R_IsBuffered = '0' and I_Valid = '1' then
                R_IsBuffered <= '1';
            elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then
                R_IsBuffered <= '0';
            end if;
        end if;
    end if;
end process;

This architecture is especially suited for deep pipeline systems with timing bottlenecks on ready.

No overhead – just data flow.