0xMax42 - Flatfile purist. Autodidact. Systems thinker.

HTTP Kernel v0.2.0 – From Dynamic Dispatch to a Pre‑Compiled Pipeline

Tue, 27 May 2025 13:00:00 +0000

With v0.2.0, my Deno‑based HTTP kernel has taken a decisive step forward: instead of chaining every middleware dynamically for each request, the entire chain is now compiled once. This reduces overhead, simplifies error handling—and makes routing noticeably faster.

Baseline

The first generation of the kernel relied on a recursive dispatch() mechanism:

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private async executePipeline(
 ctx: TContext,
 middleware: Middleware<TContext>[],
 handler: Handler<TContext>,
): Promise<Response> {
 const handleInternalError = (ctx: TContext, err?: unknown) =>
 this.cfg.httpErrorHandlers[HTTP_500_INTERNAL_SERVER_ERROR](
 ctx,
 normalizeError(err),
 );

 let lastIndex = -1;

 const dispatch = async (currentIndex: number): Promise<Response> => {
 if (currentIndex <= lastIndex) {
 throw new Error('Middleware called `next()` multiple times');
 }
 lastIndex = currentIndex;

 const isWithinMiddleware = currentIndex < middleware.length;
 const fn = isWithinMiddleware ? middleware[currentIndex] : handler;

 if (isWithinMiddleware) {
 if (!isMiddleware(fn)) {
 throw new Error('Expected middleware function, but received invalid value');
 }
 return await fn(ctx, () => dispatch(currentIndex + 1));
 }

 if (!isHandler(fn)) {
 throw new Error('Expected request handler, but received invalid value');
 }

 return await fn(ctx);
 };

 try {
 const response = await dispatch(0);
 return this.cfg.decorateResponse(response, ctx);
 } catch (e) {
 return handleInternalError(ctx, e);
 }
}

This approach was easy to understand, but for each request it created several closures, index checks and type checks – all things that waste precious time under high concurrency.

The new approach

When registering a route, a statically linked chain of functions is now generated. The result is a single function runRoute(ctx) that inlines all middlewares and the handler.

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private compile(
 route: Omit<IInternalRoute<TContext>, 'runRoute' | 'matcher' | 'method'>,
): (ctx: TContext) => Promise<Response> {
 if (!isHandler<TContext>(route.handler)) {
 throw new TypeError('Route handler must be a function returning a Promise<Response>.');
 }
 let composed = route.handler;

 for (let i = route.middlewares.length - 1; i >= 0; i--) {
 if (!isMiddleware<TContext>(route.middlewares[i])) {
 throw new TypeError(`Middleware at index ${i} is not a valid function.`);
 }

 const current = route.middlewares[i];
 const next = composed;

 composed = async (ctx: TContext): Promise<Response> => {
 let called = false;
 return await current(ctx, async () => {
 if (called) {
 throw new Error(`next() called multiple times in middleware at index ${i}`);
 }
 called = true;
 return await next(ctx);
 });
 };
 }

 return composed;
}

Important: every middleware still receives its next() function – but thanks to the called flag it can now be invoked only once, reliably preventing multiple executions.

Benchmarks

Measured with 10 000 parallel requests on a Ryzen 7 8845HS:

Benchmark (parallel)	v0.1.0 (dynamic)	v0.2.0 (pre‑compiled)	Gain
Simple Route	5.4 ms	2.1 ms	≈ 61 %
Complex Route	11.2 ms	7.9 ms	≈ 29 %

For single requests, the numbers are almost identical – the speed advantage becomes apparent mainly under heavy load.

Conclusion

Static routing reduces overhead and significantly increases throughput.
next() errors are now detected immediately.
The API remained compatible – upgrading from 0.1.x to 0.2.0 requires no code changes.

The kernel is already running fast and stable in my build‑cache‑server – a Deno‑based build cache for act; compatible with the GitHub Actions Cache API.

👉 Source code & release notes: https://github.com/0xMax42/http-kernel

Creating systemd Timers via CLI – Simple, Fast, Hassle-Free

Sat, 24 May 2025 21:30:00 +0000

If you’ve ever tried writing systemd timers by hand, you know: it’s not exactly fun. Between .service and .timer files, path syntax, and OnCalendar expressions, it’s easy to get lost. That’s why I built a small tool: systemd-timer.

What does it do?

It’s simple: You call a CLI command, provide a few arguments, and the tool writes the appropriate .service and .timer files for you — with logging, dependencies, and all the systemd details you’d otherwise have to remember. No copy-pasting templates, no typos, no wondering whether it’s WantedBy=timers.target or not.

Why not just use `cron`?

Sure, cron works. But systemd has some clear advantages:

Better logging (including to file)
Easier integration with other services (like waiting for network)
Works per-user (no root needed)
Everything stays in one ecosystem: systemd

This CLI lowers the entry barrier while still encouraging “proper” systemd usage.

What can `systemd-timer` do?

Generates .service + .timer unit files
Supports --user timers (great for desktop or containers)
Logging to file via --logfile
Standard options like:
- --exec, --calendar, --after, --environment
- --description, --output, --dry-run
CLI built with Cliffy, typed with Deno
Platform-independent install via shell script

A quick example

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systemd-timer create \
 --exec "/usr/local/bin/backup.sh" \
 --calendar "Mon..Fri 02:00" \
 --description "Backup Job" \
 --user \
 --logfile "/var/log/backup.log"

This creates:

~/.config/systemd/user/backup.service
~/.config/systemd/user/backup.timer

To activate:

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systemctl --user daemon-reload
systemctl --user enable --now backup.timer

One-liner install

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curl -fsSL https://git.0xmax42.io/maxp/systemd-timer/raw/branch/main/scripts/install.sh | sh

The script auto-detects your architecture (amd64/arm64), fetches the right binary, and verifies it via SHA256. And yes, you can inspect the code before piping it into your shell.

Development & testing

The tool is written entirely in TypeScript with Deno, strictly typed and covered by tests. The core is modular enough that you could use it as a library if needed.

Run tests with:

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deno task test

Conclusion

systemd-timer isn’t a monster with 1000 options — it’s just what you want when you need a clean way to run small systemd-timed tasks without rewriting the same files over and over. It’s aimed at people who prefer declarative setups over improvisation.

Source code, releases, and more: 👉 git.0xmax42.io/maxp/systemd-timer

PyDEPP: Python Meets FPGA

Thu, 24 Apr 2025 09:16:09 +0000

I’ve released a new open-source project: PyDEPP – a Python library for communicating with Digilent FPGA boards via the DEPP protocol. The goal was to create a modern, object-oriented interface for accessing registers, data streams, and debugging functions, built directly on top of Digilent’s Adept SDK.

Why this project?

Digilent’s DEPP protocol is powerful, but its native interface is rather clunky. If you’ve ever worked with the C APIs, you know it could be more elegant. PyDEPP abstracts this complexity and brings register and stream access to Python-level simplicity – including context management via with, flexible timeout control, and debug dumps.

Highlights:

get_reg() / set_reg() – easy register access
put_stream() / get_stream() – efficient data transfer
Customizable timeouts
Context manager for clean resource handling
Register dumps for debugging

The library is fully open source and MIT licensed. If you’re into Python-based hardware communication, this is for you.

Tested with:

Digilent Nexys2 FPGA board
Python 3.11 on Debian
Shared libraries: libdmgr.so, libdepp.so from the Adept SDK

➡️ If you’re interested in embedded development with Python or want to make better use of the DEPP interface, you’re welcome to join in.

Optimizing the Pipeline

Tue, 22 Apr 2025 09:32:40 +0000

Today I’m focusing on optimizing a small pipeline I created for a project. The pipeline is responsible for calculating the address offset of a sprite and checking whether it’s visible in the currently requested line.

So far, I’ve relied on register rebalancing to do the job. This does work, but of course, there’s still room for optimization.

Here’s the current code as a starting point:

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.SpriteRom.all;

entity VerticalSpritePipeline is
 generic (
 --@ Width of the Y position (Line) register
 G_Y_Width : integer := 10;
 --@ The height of the sprite in pixels
 G_Sprite_Height : integer := 16;
 --@ Width of the sprite offset (Line address) register
 G_Offset_Width : integer := 8;
 --@ The pipeline stages for the calculating pipeline (multiply by 2 for the the latency of the pipeline)
 G_PipelineStages : integer := 2
 );
 port (
 --@ Clock signal; (**Rising edge** triggered)
 I_CLK : in std_logic := '0';
 --@ Clock enable signal (**Active high**)
 I_CE : in std_logic := '1';

 --@ @virtualbus VSpritePipeline-OP @dir In Vertical sprite pipeline operation interfacee
 --@ AXI like ready; (**Synchronous**, **Active high**)
 O_VSpritePipeline_OP_Ready : out std_logic := '0';
 --@ AXI like valid; (**Synchronous**, **Active high**)
 I_VSpritePipeline_OP_Valid : in std_logic := '0';
 --@ The line to check if the sprite is in the line visible.
 I_VSpritePipeline_OP_Y_Request : in std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 --@ The sprite Y position to check if the sprite is in the line visible.
 I_VSpritePipeline_OP_Y_Sprite : in std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 --@ @end

 --@ @virtualbus VSpritePipeline-Result @dir Out Vertical sprite pipeline result interface
 --@ AXI like ready; (**Synchronous**, **Active high**)
 I_VSpritePipeline_Ready : in std_logic := '0';
 --@ AXI like valid; (**Synchronous**, **Active high**)
 O_VSpritePipeline_Valid : out std_logic := '0';
 --@ Indicates if the sprite is visible in the line.
 O_VSpritePipeline_IsVisible : out std_logic := '0';
 --@ The calculated offset address of the sprite.
 O_VSpritePipeline_Offset : out std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0')
 --@ @end
 );
end entity VerticalSpritePipeline;

architecture Rtl of VerticalSpritePipeline is
 --@ Line to check if the sprite is in the line visible
 signal R_Y_Request : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 --@ The sprite Y position to check if the sprite is in the line visible
 signal R_Y_Sprite : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');

 --@ Calculated visibility signal
 signal C_IsVisible : std_logic := '0';
 --@ The calculated offset address of the sprite
 signal C_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');

 --@ Pipeline enable signal
 signal S_CalculatingPipeline_Enable : std_logic := '0';
begin

 --@ Pipeline controller for the calculating pipeline
 I_CalculatingPipelineCtrl : entity work.PipelineController
 generic map(
 G_PipelineStages => G_PipelineStages * 2
 )
 port map(
 I_CLK => I_CLK,
 I_CE => I_CE,
 O_Enable => S_CalculatingPipeline_Enable,
 I_Valid => I_VSpritePipeline_OP_Valid,
 O_Ready => O_VSpritePipeline_OP_Ready,
 O_Valid => O_VSpritePipeline_Valid,
 I_Ready => I_VSpritePipeline_Ready
 );

 --@ Input register for the Y position of the sprite
 I_Y_InputRegister : entity work.PipelineRegister
 generic map(
 G_PipelineStages => G_PipelineStages,
 G_Width => G_Y_Width,
 G_RegisterBalancing => "forward"
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => S_CalculatingPipeline_Enable,
 I_Data => I_VSpritePipeline_OP_Y_Sprite,
 O_Data => R_Y_Sprite
 );

 --@ Input register for the line to check if the sprite is in the line visible
 I_YToCheck_InputRegister : entity work.PipelineRegister
 generic map(
 G_PipelineStages => G_PipelineStages,
 G_Width => G_Y_Width,
 G_RegisterBalancing => "forward"
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => S_CalculatingPipeline_Enable,
 I_Data => I_VSpritePipeline_OP_Y_Request,
 O_Data => R_Y_Request
 );

 --@ Combinatory process to calculate the visibility and offset of the sprite.
 P_CalculateVisibility : process (R_Y_Sprite, R_Y_Request)
 variable V_Y_Sprite : unsigned(R_Y_Sprite'range);
 variable V_Y_Request : unsigned(R_Y_Request'range);
 variable V_SpriteYBottom : unsigned(R_Y_Sprite'range);
 variable V_OffsetLine : integer;
 variable V_Offset : unsigned(C_Offset'range);
 begin
 V_Y_Sprite := unsigned(R_Y_Sprite);
 V_Y_Request := unsigned(R_Y_Request);
 V_SpriteYBottom := V_Y_Sprite + to_unsigned(G_Sprite_Height - 1, R_Y_Sprite'length);

 if V_Y_Request >= V_Y_Sprite and
 V_Y_Request <= V_SpriteYBottom then
 C_IsVisible <= '1';
 else
 C_IsVisible <= '0';
 end if;

 V_OffsetLine := to_integer(V_Y_Request - V_Y_Sprite);
 -- pragma translate_off
 if V_OffsetLine < 0 or V_OffsetLine >= K_SPRITE_ROW_OFFSETS'length then
 V_OffsetLine := 0;
 end if;
 -- pragma translate_on

 V_Offset := to_unsigned(K_SPRITE_ROW_OFFSETS(V_OffsetLine), C_Offset'length);
 C_Offset <= std_logic_vector(V_Offset);
 end process;

--@ Output register for the visibility of the sprite
 I_IsVisible_OutputRegister : entity work.PipelineRegister
 generic map(
 G_PipelineStages => G_PipelineStages,
 G_Width => 1,
 G_RegisterBalancing => "backward"
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => S_CalculatingPipeline_Enable,
 I_Data(0) => C_IsVisible,
 O_Data(0) => O_VSpritePipeline_IsVisible
 );

--@ Output register for the offset of the sprite
 I_Offset_OutputRegister : entity work.PipelineRegister
 generic map(
 G_PipelineStages => G_PipelineStages,
 G_Width => G_Offset_Width,
 G_RegisterBalancing => "backward"
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => S_CalculatingPipeline_Enable,
 I_Data => C_Offset,
 O_Data => O_VSpritePipeline_Offset
 );
end architecture;

As you can see, the splitting of the computation is currently left entirely to the synthesis. Now it’s about finding a performance-optimized breakdown of the logic.

Within the calculation process, we find two relevant calculations and one comparison:

Calculate the bottom edge of the sprite:

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V_SpriteYBottom := V_SpriteY + to_unsigned(G_Sprite_Height - 1, R_Y_Sprite'length);

Visibility check:

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if V_YToCheck >= V_SpriteY and
 V_YToCheck <= V_SpriteYBottom then

Calculate the address offset:

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V_OffsetLine := to_integer(V_YToCheck - V_SpriteY);

Since operations 2 and 3 depend on the result of the first, we’ll perform that one in a separate stage.

To prepare, we’ll first refactor the registers. We’ll rename them and switch from dynamically to statically defined pipeline stages.

We modify the pipeline controller as follows:

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 INST_VSpritePipeline_Ctrl : entity work.PipelineController
 generic map(
 G_PipelineStages => 3 -- TODO
 )
 port map(
 I_CLK => I_CLK,
 I_CE => I_CE,
 O_Enable => O_VSpritePipelineCtrl_Enable,
 I_Valid => I_VSpritePipeline_OP_Valid,
 O_Ready => O_VSpritePipeline_OP_Ready,
 O_Valid => O_VSpritePipeline_Valid,
 I_Ready => I_VSpritePipeline_Ready
 );

We also reduce the input registers to a single stage:

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 INST0_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data => I_VSpritePipeline_OP_Y_Sprite,
 O_Data => R0_Y_Sprite
 );

 INST0_VSpritePipeline_Y_Request : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data => I_VSpritePipeline_OP_Y_Request,
 O_Data => R0_Y_Request
 );

We introduce new combinatory and registered signals C_Y_Bottom_Sprite and R_Y_Bottom_Sprite and calculate the first stage using a concurrent signal assignment to avoid embedding this logic in a process:

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 --@ Calculate the bottom Y position of the sprite
 C_Y_Bottom_Sprite <= std_logic_vector(
 unsigned(R_Y_Sprite) + to_unsigned(G_Sprite_Height - 1, G_Y_Width)
 );

And we need a register for the result:

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 INST_VSpritePipeline_Y_Bottom_Sprite : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data => C_Y_Bottom_Sprite,
 O_Data => R_Y_Bottom_Sprite
 )

To carry forward base values, we introduce additional registers:

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 INST1_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data => R0_Y_Sprite,
 O_Data => R1_Y_Sprite
 );

 INST1_VSpritePipeline_Y_Request : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data => R0_Y_Request,
 O_Data => R1_Y_Request
 );

With the registered signals R1_Y_Sprite, R1_Y_Request, and R_Y_Bottom_Sprite in the next stage, we can now perform operations 2 and 3 in parallel:

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 --@ Calculate the visibility of the sprite
 C_IsVisible <= '1' when (
 (unsigned(R1_Y_Request) >= unsigned(R1_Y_Sprite)) and
 (unsigned(R1_Y_Request) <= unsigned(R_Y_Bottom_Sprite))
 ) else '0';

 --@ Calculate the offset address of the sprite
 C_Offset <= std_logic_vector(
 to_unsigned(
 K_SPRITE_ROW_OFFSETS(to_integer(unsigned(R1_Y_Request) - unsigned(R1_Y_Sprite))),
 C_Offset'length)
 );

Finally, we store these values in the output registers:

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 INST_IsVisible_OutputRegister : entity work.PipelineRegister
 generic map(
 G_Width => 1
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data(0) => C_IsVisible,
 O_Data(0) => O_VSpritePipeline_IsVisible
 );

 INST_Offset_OutputRegister : entity work.PipelineRegister
 generic map(
 G_Width => G_Offset_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipelineCtrl_Enable,
 I_Data => C_Offset,
 O_Data => O_VSpritePipeline_Offset
 );

The only remaining change is setting G_PipelineStages to 3, which we’ve already done at the top. We can now remove the -- TODO comment.

The code now looks like this:

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.SpriteRom.all;

entity VerticalSpritePipeline is
 generic (
 --@ Width of the Y position (Line) register
 G_Y_Width : integer := 10;
 --@ The height of the sprite in pixels
 G_Sprite_Height : integer := 16;
 --@ Width of the sprite offset (Line address) register
 G_Offset_Width : integer := 8;
 --@ The pipeline stages for the calculating pipeline (multiply by 2 for the the latency of the pipeline)
 G_PipelineStages : integer := 2
 );
 port (
 --@ Clock signal; (**Rising edge** triggered)
 I_CLK : in std_logic := '0';
 --@ Clock enable signal (**Active high**)
 I_CE : in std_logic := '1';

 --@ @virtualbus VSpritePipeline-OP @dir In Vertical sprite pipeline operation interfacee
 --@ AXI like ready; (**Synchronous**, **Active high**)
 O_VSpritePipeline_OP_Ready : out std_logic := '0';
 --@ AXI like valid; (**Synchronous**, **Active high**)
 I_VSpritePipeline_OP_Valid : in std_logic := '0';
 --@ The line to check if the sprite is in the line visible.
 I_VSpritePipeline_OP_Y_Request : in std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 --@ The sprite Y position to check if the sprite is in the line visible.
 I_VSpritePipeline_OP_Y_Sprite : in std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 --@ @end

 --@ @virtualbus VSpritePipeline-Result @dir Out Vertical sprite pipeline result interface
 --@ AXI like ready; (**Synchronous**, **Active high**)
 I_VSpritePipeline_Ready : in std_logic := '0';
 --@ AXI like valid; (**Synchronous**, **Active high**)
 O_VSpritePipeline_Valid : out std_logic := '0';
 --@ Indicates if the sprite is visible in the line.
 O_VSpritePipeline_IsVisible : out std_logic := '0';
 --@ The calculated offset address of the sprite.
 O_VSpritePipeline_Offset : out std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0')
 --@ @end
 );
end entity VerticalSpritePipeline;

architecture Rtl of VerticalSpritePipeline is
 --@ Line to check if the sprite is in the line visible
 signal R0_Y_Request : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 signal R1_Y_Request : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 --@ The sprite Y position to check if the sprite is in the line visible
 signal R0_Y_Sprite : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 signal R1_Y_Sprite : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');

 --@ The bottom Y position of the sprite
 signal C_Y_Bottom_Sprite : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
 signal R_Y_Bottom_Sprite : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');

 --@ Calculated visibility signal
 signal C_IsVisible : std_logic := '0';
 --@ The calculated offset address of the sprite
 signal C_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');

 --@ Pipeline enable signal
 signal O_VSpritePipeline_Ctrl_Enable : std_logic := '0';
begin
 INST_VSpritePipeline_Ctrl : entity work.PipelineController
 generic map(
 G_PipelineStages => 3
 )
 port map(
 I_CLK => I_CLK,
 I_CE => I_CE,
 O_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Valid => I_VSpritePipeline_OP_Valid,
 O_Ready => O_VSpritePipeline_OP_Ready,
 O_Valid => O_VSpritePipeline_Valid,
 I_Ready => I_VSpritePipeline_Ready
 );

 INST0_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data => I_VSpritePipeline_OP_Y_Sprite,
 O_Data => R0_Y_Sprite
 );

 INST0_VSpritePipeline_Y_Request : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data => I_VSpritePipeline_OP_Y_Request,
 O_Data => R0_Y_Request
 );

 --@ Calculate the bottom Y position of the sprite
 C_Y_Bottom_Sprite <= std_logic_vector(
 unsigned(R0_Y_Sprite) + to_unsigned(G_Sprite_Height - 1, G_Y_Width)
 );

 INST_VSpritePipeline_Y_Bottom_Sprite : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data => C_Y_Bottom_Sprite,
 O_Data => R_Y_Bottom_Sprite
 );

 INST1_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data => R0_Y_Sprite,
 O_Data => R1_Y_Sprite
 );

 INST1_VSpritePipeline_Y_Request : entity work.PipelineRegister
 generic map(
 G_Width => G_Y_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data => R0_Y_Request,
 O_Data => R1_Y_Request
 );

 --@ Calculate the visibility of the sprite
 C_IsVisible <= '1' when (
 (unsigned(R1_Y_Request) >= unsigned(R1_Y_Sprite)) and
 (unsigned(R1_Y_Request) <= unsigned(R_Y_Bottom_Sprite))
 ) else '0';

 --@ Calculate the offset address of the sprite
 C_Offset <= std_logic_vector(
 to_unsigned(
 K_SPRITE_ROW_OFFSETS(to_integer(unsigned(R1_Y_Request) - unsigned(R1_Y_Sprite))),
 C_Offset'length)
 );

 INST_IsVisible_OutputRegister : entity work.PipelineRegister
 generic map(
 G_Width => 1
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data(0) => C_IsVisible,
 O_Data(0) => O_VSpritePipeline_IsVisible
 );

 INST_Offset_OutputRegister : entity work.PipelineRegister
 generic map(
 G_Width => G_Offset_Width
 )
 port map(
 I_CLK => I_CLK,
 I_Enable => O_VSpritePipeline_Ctrl_Enable,
 I_Data => C_Offset,
 O_Data => O_VSpritePipeline_Offset
 );
end architecture;

Compared to the previous version, we now have a pre-processing calculation (stage 1) and have parallelized the visibility and offset calculations (stage 2). This should provide a slight performance improvement. In my overall design, the pipeline has gone from being a bottleneck to a timing-irrelevant component.

During synthesis (pre place & route), we achieved a significant improvement on the used Spartan 3:

Before: Minimum period: 5.739ns (Max Frequency: 174.246MHz)
After: Minimum period: 4.857ns (Max Frequency: 205.888MHz)

Thus, we’ve successfully accelerated the pipeline and simplified the code.

Minimal Skidbuffer with AXI-like Handshaking

Sat, 19 Apr 2025 19:14:03 +0000

Created in less than an hour:
A compact skidbuffer that only decouples the ready signal – with zero added latency.

The background here is the use of AXI-like handshaking and the need to decouple the ready signal in order to optimize data processing. In the desisngs I use, the ready signal is often the bottleneck, as it usually has to be propagated through several pipelines. A skid buffer can help here to reduce latency and optimize data processing. In contrast, the ‘valid’ signal is not decoupled as it is decoupled by each pipeline itself.

Translated with DeepL.com (free version)

The design follows a simple principle:

If ready = '1', the signal is passed through directly (MUX = 0)
If ready = '0', a buffer is activated (MUX = 1)
valid is either forwarded directly or taken from the buffer

The system implements complete AXI-like handshaking
and was successfully tested with randomly delayed upstream and downstream.

Resource usage (after synthesis, Xilinx Spartan-3):

1 flip-flop
4 LUTs
0 added latency

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--@ Set mux to buffered mode if data is available in the buffer.
C_MUX <= R_IsBuffered;
--@ Enable the buffer register if not buffered and chip enable is high.
C_Enable <= I_CE and not R_IsBuffered;
--@ Set the ready signal to high if not buffered.
O_Ready <= not R_IsBuffered;
--@ Set the valid signal to high if data is available in the buffer or if data is valid.
O_Valid <= R_IsBuffered or I_Valid;

process (I_CLK)
begin
 if rising_edge(I_CLK) then
 if I_RST = G_ResetActiveAt then
 R_IsBuffered <= '0';
 elsif I_CE = '1' then
 if R_IsBuffered = '0' and I_Valid = '1' then
 R_IsBuffered <= '1';
 elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then
 R_IsBuffered <= '0';
 end if;
 end if;
 end if;
end process;

This architecture is especially suited for deep pipeline systems with timing bottlenecks on ready.

No overhead – just data flow.

Custom Gitea Pages Stack with Wildcard Subdomains and ACME – My GitHub Pages Replacement

Sat, 19 Apr 2025 00:00:00 +0000

Introduction

This post documents my custom Gitea Pages stack – a privacy-friendly alternative to GitHub Pages. With GT-RUNNER, the Codeberg Pages server, and Traefik as a reverse proxy, I’ve built a self-managed hosting stack that fully automates domain management, TLS certificates, and deployment – without centralized dependencies and with complete control.

Architecture Overview

The following diagram shows the structure of my stack. All core components – Gitea, the runner, the Pages server, and the reverse proxy – are connected within a private network. TLS certificates are issued in two stages using Let’s Encrypt (Staging internally, Production externally):

Detailed Functionality

To be honest: at its core, it’s just a normal Git server. Gitea runs internally, and the GT-RUNNER is connected – based on act with a fairly large image that provides everything GitHub Actions does. For my use case, that’s more than compatible enough.

Next is the Codeberg Pages server – also internal. It communicates with Gitea via API, just as intended. Important: everything Gitea, the runner, and the Pages server do happens strictly inside the private network. Nothing leaks outside. That was important to me.

Now about TLS: the Pages server can’t operate without certificates. So it gets them – in the standard way via my DNS provider, through its API and the ACME protocol. But only using Let’s Encrypt’s staging certificates. Why? Because that’s enough. This is about internal TLS, not external trust.

Once the Pages server has its certs, it can serve content cleanly – internally, over HTTPS, with a proper structure. My reverse proxy (Traefik) takes care of the rest.

Traefik is configured to not care whether the internal cert is trusted. It terminates TLS on the public side, fetches valid production certificates via DNS-01 and Let’s Encrypt, and rewrites the domain paths accordingly.

To make this work, I rewrite the requests. For example, Traefik receives something like home.pagessub.0xmax42.io, extracts which repository it’s supposed to serve, and rewrites the request internally to user.pagessub.0xmax42.io/repo/. This lets the Pages server route the request correctly.

From the outside, everything looks just like GitHub Pages – every subdomain serves its own static project. But this time: privacy-friendly, self-hosted, and with no vendor lock-in.

Outlook

In the long term, I want repositories to define their own deployment domains – e.g. via a .traffic file. The Gitea API could then automatically generate the corresponding Traefik config and hand it off. The goal: a fully automated, self-healing static web hosting stack.

Components Used

🧃 Gitea – Self-hosted Git service
🌀 Traefik – Reverse proxy with ACME support
📦 Codeberg Pages Server – Static pages server
🔀 traefik-subdomain-path-rewrite-plugin – For dynamic URL rewriting based on subdomains
🔐 Let’s Encrypt – Free TLS certificate management via ACME
🐳 Docker – Containerization of all components for easy management and isolation

📁 This setup is part of my infrastructure foundation for 0xMax42.io. More posts to follow.

I'm Back!

Thu, 17 Apr 2025 00:00:00 +0000

I’m back – with a new name, new clarity, and a new digital home.
From now on, you’ll find me here as 0xMax42.

This site is more than just a blog. It’s my space for ideas, systems, thoughts – and sometimes resistance.
Everything you see here comes directly from me – independent, transparent, and without detours.

Welcome to 0xMax42.

Links

Mon, 01 Jan 0001 00:00:00 +0000

PGP

Mon, 01 Jan 0001 00:00:00 +0000

You can copy my public key here:

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Mon, 01 Jan 0001 00:00:00 +0000

0xMax42 - Flatfile purist. Autodidact. Systems thinker.

HTTP Kernel v0.2.0 – From Dynamic Dispatch to a Pre‑Compiled Pipeline

Baseline

The new approach

Benchmarks

Conclusion

Creating systemd Timers via CLI – Simple, Fast, Hassle-Free

What does it do?

Why not just use cron?

What can systemd-timer do?

A quick example

One-liner install

Development & testing

Conclusion

PyDEPP: Python Meets FPGA

Optimizing the Pipeline

Minimal Skidbuffer with AXI-like Handshaking

Custom Gitea Pages Stack with Wildcard Subdomains and ACME – My GitHub Pages Replacement

Introduction

Architecture Overview

Detailed Functionality

Outlook

Components Used

I'm Back!

Archives

Links

PGP

Search

Why not just use `cron`?

What can `systemd-timer` do?